1. Field of the Invention
The present invention relates to a semiconductor nonvolatile RAM, and, more specifically, to a chip on which both a DRAM (dynamic random access memory) as a RAM (random access memory), and an E.sup.2 PROM (electrical erasable read only memory) as a nonvolatile memory are arranged.
2. Description of the Related Art
FIG. 12 is a diagram showing a cross section of a conventional nonvolatile RAM in which a DRAM cell and an E.sup.2 PROM cell are mixedly arranged, and FIG. 13 shows an equivalent circuit of this conventional RAM.
A transistor T1, which is turned ON/OFF by a potential of a select gate SG corresponding to a word line, serves to selectively connect a drain D (n.sup.+) corresponding to a bit line and a memory node NP of the DRAM cell with each other. A transistor T2 serves to connect the transistor T1 and a transistor T3, which is a part of the E.sup.2 PROM cell, together.
A capacitor of the DRAM cell includes a memory node NP connected to a source of the transistor T1, and a control gate CG. The control gate CG serves as a plate electrode, and is controlled by means of a pulse in a store mode for transferring data from the DRAM cell to the E.sup.2 PROM cell, and in the recall mode for transferring data from the E.sup.2 PROM cell to the DRAM cell.
A nonvolatile RAM having the above-described structure, when operated as a regular DRAM, serves as a stack-type cell. In other words, both a recall gate RG and the control gate CG of the transistor T2 are grounded so that the control gate CG serve as a plate electrode, and the storage capacitor of the DRAM is the capacity between the control gate CG and the memory node NP. Since the recall gate RG is ground, the DRAM and E.sup.2 PROM cells are separated from each other. The basic operation of the DRAM, including writing, reading-out, refreshing, etc. is the same as that of regular DRAM cells.
The following is an explanation of the operation of the store mode for transferring data stored in the DRAM cell to the E.sup.2 PROM cell.
As can be seen in FIG. 14, the operation of the store mode can be divided into two, the first half and the last half.
The first half of the operation is an erasing process which writes the data of the DRAM cell, which stores data "0", in the E.sup.2 PROM cell. Electrons are emitted from the floating gate FG of the corresponding E.sup.2 PROM cell. As shown in the FIG. 14, the control gate CG and the source S are biased to the potentials of the ground and the power source Vp, respectively. Between the control gate CG and the source S, provided are the memory node NP serving as a floating node and the floating gate FG, which are capacitive-coupled with each other between the ground potential and the power source Vp.
When data "0" is stored in the DRAM cell, the memory capacitor between the control gate CG and the memory node NP is not charged, whereas when data "1" is stored therein, the storage capacitor is charged with "+" electrical charges. Consequently, while the control gate CG and the source S are biassed to the ground potential and the power source voltage Vp, respectively, a weak electrical field is applied onto the thin tunnel oxidation film located between the floating gate FG and the source S in the E.sup.2 PROM cell, when data "1" is stored in the DRAM cell. In contrast, under the same condition, the intensity of the electrical filed applied to the thin tunnel oxidation film in the DRAM cell, when data "0" is stored, is high. Therefore, only in the latter case, an F-N (Fowler-Nordheim) current flows in the E.sup.2 PROM, and electrons are discharged from the floating gate FG.
The last half of the store mode is a programming process in which electrons are injected to the floating gate of the E.sup.2 PROM cell so as to write data of the DRAM cell storing data "1" into the E.sup.2 PROM. As can be understood from FIG. 14, the control gate CG and the source S are biassed to the power source voltage Vp and the ground potential, respectively, and therefore the electrical field applied onto the tunnel oxidation film provided between the floating gate FG and the source S is weak in the case of DRAM "0" and strong in the case of DRAM "1". Thus, only in the latter case, an F-N current flows through the E.sup.2 PROM cell in the direction opposite to that of the erasing process, and electrons are injected to the floating gate FG for programming.
The following is an explanation of the recall mode for transferring data stored in the E.sup.2 PROM cell to the DRAM cell with reference to FIG. 15.
First, a drain D=5V and a select gate SG=8V are set, and data "1" is written in every DRAM cell. Then, a recall gate RG is set to 8V. At the recall gate RG=8V, the threshold level of the transistor in the E.sup.2 PROM, when data "0" is stored therein, is low, and therefore the transistor is set in a depletion mode, whereas that of the E.sup.2 PROM, when data "1" is stored therein, is high, and therefore the transistor is set in an enhance mode. Accordingly, electrical charges accumulated in the DRAM cell connected to the E.sup.2 PROM cell, when data "0" is stored therein, are discharged to the source terminal of the E.sup.2 PROM through the transistors T2 and T3, turned on by the recall gate RG. In contrast, charges in the DRAM cell connected to the E.sup.2 PROM cell, when data "1" is stored therein, remain in the DRAM cell without being discharged. Consequently, data stored in the E.sup.2 PROM is thus transferred to the DRAM cell.
In the meantime, conventional nonvolatile RAM cells are those which consist of DRAM cells and E.sup.2 PROM cells effectively mixed thereon. However, these cells have a structure in which three transistors T1, T2, and T3 are arranged in the same plane, as can be seen in FIG. 12. As a result, the occupied area in a cell is significantly larger than that of a regular DRAM or E.sup.2 PROM.